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te3-liu? line interface unit for ds3, sts1 and e3 pef 3452 version 1.3 preliminary data sheet, ds1, december 2001 wired communications never stop thinking.
edition 2001-12-05 published by infineon technologies ag, st.-martin-strasse 53, d-81669 mnchen, germany ? infineon technologies ag 2001. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
wired communications p r e l i m i n a r y te3-liu? line interface unit for ds3, sts1 and e3 pef 3452 version 1.3 preliminary data sheet, ds1, december 2001 never stop thinking.
for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com pef 3452 preliminary revision history: 2001-12-05 ds1 previous version: preliminary data sheet te3-liu v1.2, 2001-07, ds3 page subjects (major changes since last revision) 24 chapter 4.1.4 27 table 10 28 figure 12
pef 3452 te3-liu v1.3 table of contents page preliminary data sheet 2001-12-05 1 overview ................................................... 1 1.1 features.................................................... 2 1.2 logicsymbol ................................................ 4 1.3 typicalapplications ........................................... 5 2 pin descriptions ............................................ 7 2.1 pindiagram ................................................. 7 2.2 pindefinitionsandfunctions ................................... 8 3 functional description ...................................... 16 3.1 functionaloverview ......................................... 16 3.2 blockdiagram .............................................. 17 3.3 functionalblocks............................................ 18 3.3.1 hardwarecontrolunit ...................................... 18 4 interface description ........................................ 21 4.1 receiver................................................... 21 4.1.1 standard receiver application ............................... 21 4.1.2 linemonitoringapplication .................................. 22 4.1.3 receivelineinterface ...................................... 23 4.1.4 receiveclockanddatarecovery ............................ 24 4.1.5 receivelinecoding ....................................... 24 4.1.5.1 amicode.............................................. 24 4.1.5.2 b3zscode ............................................ 24 4.1.5.3 hdb3code ............................................ 25 4.1.6 alarmhandling ........................................... 25 4.1.6.1 ds3losdefinition ...................................... 25 4.1.6.2 sts-1losdefinition .................................... 25 4.1.6.3 e3losdefinition ....................................... 26 4.1.7 jittertolerance ........................................... 27 4.1.8 receiveoutputjitter ....................................... 28 4.2 transmitter................................................. 29 4.2.1 transmitlineinterface ..................................... 29 4.2.2 transmitclocksystem ..................................... 30 4.2.3 jitterattenuation .......................................... 31 4.2.4 intrinsicjitter ............................................. 32 4.2.5 pulseshaper ............................................. 33 4.2.6 transmitlinecoding....................................... 33 4.2.6.1 amicode.............................................. 33 4.2.6.2 b3zscode ............................................ 33 4.2.6.3 hdb3code ............................................ 33 4.2.7 aisinsertion ............................................. 34 4.3 framerinterface ............................................ 34 4.4 maintenance functions . ...................................... 35
pef 3452 te3-liu v1.3 table of contents page preliminary data sheet 2001-12-05 4.4.1 remote loop . ............................................ 35 4.4.2 localloop ............................................... 36 5 operational description ..................................... 37 5.1 operationaloverview ........................................ 37 5.2 devicereset ............................................... 37 5.3 devicepowerdown ......................................... 37 5.4 transmitlineinactive ........................................ 37 6 electrical characteristics .................................... 38 6.1 absolutemaximumratings .................................... 38 6.2 operatingrange ........................................... 39 6.3 dccharacteristics........................................... 40 6.4 accharacteristics ........................................... 42 6.4.1 reset ................................................... 42 6.4.2 referenceclock .......................................... 43 6.4.3 jitterattenuatorreferenceclock ............................. 44 6.4.4 microprocessorcontrol ..................................... 46 6.4.5 transmit input timing ...................................... 47 6.4.6 receiveoutputtiming ..................................... 48 6.4.7 pulsetemplates .......................................... 49 6.4.7.1 pulsetemplatee3 ...................................... 49 6.4.7.2 pulsetemplateds3 ..................................... 50 6.4.7.3 pulsetemplatests-1.................................... 52 6.5 capacitances ............................................... 54 6.6 packagecharacteristics ...................................... 54 6.7 testconfiguration ........................................... 55 7 package outlines ........................................... 56 8 appendix ................................................. 57 8.1 cablecharacteristics......................................... 57 8.2 applicationexample ......................................... 58
pef 3452 te3-liu v1.3 list of figures page preliminary data sheet 2001-12-05 figure1 logicsymbol............................................. 4 figure2 t3/t1multiplexerapplication................................. 5 figure 3 channelized t3 link layer application . . ....................... 5 figure 4 unchannelized t3 link layer application ....................... 5 figure5 pinconfiguration.......................................... 7 figure6 blockdiagram........................................... 17 figure7 receiverconfiguration .................................... 21 figure8 ds3linemonitoring ...................................... 22 figure9 receiveclocksystem..................................... 23 figure 10 e3 loss of signal definition ................................. 26 figure11 jittertoleranceprinciple................................... 27 figure12 jittertolerance .......................................... 28 figure13 transmitterconfiguration .................................. 29 figure14 transmitclocksystem .................................... 30 figure15 jitterattenuationcharacteristic.............................. 32 figure 16 remote loop signal flow . ................................. 35 figure 17 local loop signal flow . . . ................................. 36 figure18 resettiming ............................................ 42 figure19 referenceclocktiming.................................... 43 figure20 xtalclocktiming ....................................... 44 figure 21 recommended crystal circuit ............................... 44 figure 22 crystal pulling range ..................................... 45 figure23 chipselecttiming........................................ 46 figure 24 xclk input timing . . ...................................... 47 figure25 rclkoutputtiming ...................................... 48 figure26 e3pulseshapeattransmitteroutput ........................ 49 figure27 ds3pulseshapeatthecrossconnectpoint(450ft.)............ 50 figure 28 sts-1 pulse shape at the cross connect point (450 ft.) .......... 52 figure 29 thermal behavior of package ............................... 54 figure30 input/outputwaveformsforactesting ....................... 55 figure31 ds3cablecharacteristics.................................. 57 figure32 applicationcircuit ........................................ 58
pef 3452 te3-liu v1.3 list of tables page preliminary data sheet 2001-12-05 table1 interfacepinfunctions ..................................... 8 table2 controlpinfunctions...................................... 11 table 3 power supply pins . . ...................................... 14 table4 testpins ............................................... 15 table5 hardwarecontrolfunctions ................................ 18 table 6 hardware indication signals ................................ 20 table 7 external component values for receiver ...................... 21 table 8 external component values for ds line monitoring .............. 22 table9 e3receivereturnloss ................................... 23 table10 inputjitterrequirements................................... 27 table 11 external component values for transmitter .................... 29 table12 e3transmitreturnloss................................... 30 table 13 jitter attenuation pll operation frequencies . . . ................ 31 table14 transmitoutputjitter ..................................... 32 table15 maximumratings ........................................ 38 table 16 power supply range ...................................... 39 table17 dcparameters .......................................... 40 table18 resettimingparametervalues ............................. 42 table19 refclktimingparametervalues........................... 43 table20 xtaltimingparametervalues ............................. 44 table21 xtalcrystalparametervalues ............................. 45 table22 chipselecttimingparametervalues......................... 46 table23 xclktimingparametervalues ............................. 47 table24 rclktimingparametervalues ............................. 48 table25 e3pulsemask........................................... 49 table 26 ds3 pulse mask (ansi t1.404, gr-499-core) ................ 50 table 27 ds3 pulse mask (ansi t1.404) . . ........................... 51 table28 ds3pulsemask(gr-499-core)............................ 51 table29 sts-1pulsemask........................................ 52 table 30 sts-1 pulse mask (ansi t1.102) . ........................... 52 table 31 pin capacitances . . . ...................................... 54 table32 packagecharacteristicvalues .............................. 54 table 33 ac test conditions . ...................................... 55
pef 3452 te3-liu v1.3 preliminary data sheet 2001-12-05 preliminary preface the pef 3452 (te3-liu?) is a flexible line interface unit for a wide area of telecommunication and data communication applications. the device is addressed to fulfill all requirements to build a ds3, sts-1 or e3 line interface. organization of this document this preliminary data sheet is organized as follows: overview gives a general description of the product, lists the key features, and presents some typical applications. pin descriptions lists pin locations with associated signals, categorizes signals according to function, and describes signals. functional description describes the functional blocks and principle operation modes. interface description describes the device interfaces. operational description shows the operation modes and how their initialization. electrical characteristics specifies maximum ratings, dc and ac characteristics. package outlines shows the mechanical values of the device package. appendix index
pef 3452 te3-liu v1.3 preliminary data sheet 2001-12-05 preliminary related documentation this document refers to the following international standards (in alphabetical/numerical order): aca ts016 (general requirements for australia) ctr-24/tbr-24 (e3 requirements) ets 300 166 (e3 transmit return loss) itu-t g.703 (e3 pulse mask, b3zs/hdb3 code, e3 receive return loss) itu-t g.751 (jitter requirements e3) itu-t g.775 (loss of signal definition) itu-t g.823 (jitter requirements e3) itu-t g.824 (jitter requirements ds3) itu-t o.151 (pseudo random binary sequence (prbs) definition) gr-253-core (sts-1 jitter requirements) gr-499-core (ds3 pulse mask, ds3 jitter requirements) ansi t1.102 (sts-1 pulse mask) ansi t1.102 annex b (ds3 monitoring) ansi t1.231 (maintenance functions, defect definitions) ansi t1.404 (ds3 pulse mask) mil-std 883d (esd requirements) your comments we welcome your comments on this document. we are continuously trying improving our documentation. please send your remarks and suggestions by e-mail to com.docu_comments@infineon.com please provide in the subject of your e-mail: device name (te3-liu?), device number (pef 3452), device version (version 1.3), and in the body of your e-mail: document type (preliminary data sheet), issue date (2001-12-05) and document revision number (ds1).
pef 3452 te3-liu v1.3 overview preliminary data sheet 1 2001-12-05 preliminary 1 overview the te3-liu? pef 3452 line interface unit is used to connect a ds3/sts-1 or e3 framer device to an analog transmission line. the line interface fulf ills the relevant standards for ds3 (44.736 mbit/s), sts-1 (51.840 mbit/s) and e3 (34.368 mbit/s) systems. thete3-liu?comesinap-m q fp-44-2 package (smd) to save a significant amount of board space. the integrated jitter attenuation further reduces overall system complexity and cost. this cmos 3.3 v low power device contains an integrated pulse shaper to drive any line length within the range of up to 1100 ft. without the need for external length selection (line build out). the hardware configuration mode allows low cost systems with flexible device setting without the need for a microprocessor. an optional microprocessor mode allows the connection to a standard microprocessor bus to control hardware settings.
preliminary data sheet 2 2001-12-05 type package pef 3452 h v1.3 p-m q fp-44-2 line interface unit for ds3, sts1 and e3 te3-liu? pef 3452 version 1.3 preliminary 1.1 features generic analog interface for all ds3/sts-1/e3 applications single chip solution for receive and transmit direction 3.3 v low power device integrated receive equalization network integrated noise and crosstalk filter clock and data recovery using an integrated pll with ultra-low intrinsic jitter transmit clock duty cycle correction pll no external components required for clock and data recovery and receive equalizer dsx receive line monitor (additional 20 db gain according to ansi t1.102) low transmitter output impedances for high transmit return loss disable function of the analog transmit line outputs transmit pulse shaper to fulfill requirements of ansi t1.404, telcordia gr-499-core, ansi t1.102 and itu-t g.703 (e3) maximum line length up to 1100 ft. (using standard coaxial cable, for example at & t 728a, 734a or 734d) external line length selection (lbo) is not required jitter specifications of gr-499-core and itu-t g.823 are met integrated jitter attenuation pll and buffer in transmit direction dual or single rail digital inputs and outputs from/to the framer interface selectable line codes (hdb3 (e3), b3zs (ds3/sts-1), ami) analog and digital loss of signal detection and indication automatic rdop/rdon blanking option in case of los bipolar violation indication local loop and remote loop for diagnostic purposes insertion of alarm indication signal ( " all ones " ) flexible hardware or software controlled device configuration device power down function p-mqfp-44-2
pef 3452 te3-liu v1.3 overview preliminary data sheet 3 2001-12-05 preliminary hardware interface mode ds3/sts-1 or e3 line coding (e3: hdb3 or ami ; ds3/sts-1: b3zs or ami) transmitter disable power down remote loop local loop single/dual rail operation receive clock edge selection transmit clock edge selection transmit " all ones " receive line monitoring mode automatic rdop/rdon blanking option jitter attenuation loss of signal indication bipolar violation indication microprocessor interface mode microprocessor bus compatible interface hardware control lines directly accessible general cmosdevice p-m q fp-44-2 package (body size 10 mm 10 mm, lead pitch 0.8 mm) single power supply: 3.3 v 5 % 5v-tolerant digital input lines temperature range of -40c to + 85c low power device applications interface for sonet/ds3 and e3 network equipment wangateways csu/dsu multiplexers digital crossconnect systems ds3/sts-1/e3 test equipment
pef 3452 te3-liu v1.3 overview preliminary data sheet 4 2001-12-05 preliminary 1.2 logic symbol figure 1 logic symbol f0229 rdop rdon/bpv rclk xdip xdin xclk los rl1 rl2 xl1 xl2 vddrp vssrp vddxp vssxp vdd vss res xais rl ll lcode dr/sr rpe xpe tdi tck tms xlt vddr vssr vddx vssx refclk cs mon xtal2 xtal1 hw + p access ble trs tdo pef 3452 te3-liu tm ds3/sts-1 ds3/e3 jatt
pef 3452 te3-liu v1.3 overview preliminary data sheet 5 2001-12-05 preliminary 1.3 typical applications figure 2 to figure 4 show typical applications using the te3-liu?. figure 2 t3/t1 multiplexer application figure 3 channelized t3 link layer application figure 4 unchannelized t3 link layer application f0087 te3-mux tm te3_liu tm ds3 analog q uadliu tm # 1 ds1 # 1 analog q uadliu tm # 7 ds1 # 28 analog ds3 digital 28 x ds1 digital f0217 te3-liu tm ds3 analog te3- chatt tm f0140 te3-liu tm ds3 analog dscc4 te3-mux tm
pef 3452 te3-liu v1.3 overview preliminary data sheet 6 2001-12-05 preliminary note: te3-mux ? (peb 3445) is an m13 mu ltiple x er/demultiplexer with an integrated ds3 framer quadliu ? (peb 22504) is a 4 -channel l ine i nterface u nit for e1/t1/j1 dscc4 ? (peb 20534) is a 4-channel s erial c ommunication c ontroller te3-chatt ? (peb 3456) is a cha nnelized t 3 t ermination with ds3 framer, m13 multiplexer, t1/e1 framers and 256 channel hdlc/ppp controller
pef 3452 te3-liu v1.3 pin descriptions preliminary data sheet 7 2001-12-05 preliminary 2 pin descriptions 2.1 pin diagram figure 5 pin configuration dr/sr lcode mon ble xais vssrp vddrp ll rl xlt los xl1 vssx xl2 ds3/sts1 ds3/e3 rpe xpe vssr rl1 rl2 vddr res xdin xclk vss vdd rclk rdop rdon/bpv cs xdip refclk vddx jatt tdo tck vssxp xtal1 xtal2 vddxp tms tdi trs pef 3452 te3-liu tm 33 23 27 31 29 25 44 34 38 42 40 36 12 22 18 14 16 20 17 35 911 f0230 p-mqfp-44-2 (top view)
pef 3452 te3-liu v1.3 pin descriptions preliminary data sheet 8 2001-12-05 preliminary 2.2 pin definitions and functions table 1 interface pin functions pin no. symbol input ( i ) output ( o ) supply ( s ) function receive direction 9 rl1 i (analog) line receiver 1 analog input from the external transformer (receive bipolar ring). the signal at rl1 must be coded according to b3zs or hdb3. 10 rl2 i (analog) line receiver 2 analog input from the external transformer (receive bipolar tip). the signal at rl1 must be coded according to b3zs or hdb3. 25 rdop o receive data output/positive received data at rl1/2 is sent on rdop/ rdon to the framer interface. data is clocked with the rising or falling edge of rclk, depending on rpe. in single rail mode (dr/sr = 0), data is sent in nrz format. 24 rdon o receive data output/negative if dual rail data format is selected, the negative data signal is output on rdon/ bpv. bpv b ipolar violation if single rail data format is selected, the bipolar violation indication signal is output on rdon/bpv. bpv is synchronized on rclk. 26 rclk o receive clock receive clock extracted from the incoming data pulses. the active clock edge is determined by rpe. during los, a clock signal is generated internally and driven on rclk (derived from refclk).
pef 3452 te3-liu v1.3 pin descriptions preliminary data sheet 9 2001-12-05 preliminary transmit direction 1 xl1 o (analog) transmit line 1 (transmit bipolar ring) analog output to the external transformer. xl1 can be switched into inactive mode. 3 xl2 o (analog) transmit line 2 (transmit bipolar tip) analog output to the external transformer. xl2 can be switched into inactive mode. 31 xdip i + pu transmit data in/positive transmit data received from the framer interface to be output on xl1/2. nrz or dual rail positive data has to be provided at xdip. latching of data is done with the rising or falling transitions of xclk, depending on xpe. 32 xdin i + pu transmit data in/negative if dual rail format is selected, negative data signal is read from xdin. if single rail data format is selected, data on xdin is ignored. latching of data is done with the rising or falling transitions of xclk, depending on xpe. 30 xclk i + pu transmit clock input of the working clock for the transmitter. the active clock edge is determined by xpe. ds3: 44.736 mhz sts-1: 51.840 mhz e3: 34.368 mhz to fulfill e.g. itu-t g.832 a clock accuracy of 20 ppm is required. for correct function a clock signal has always to be supplied to xclk. table 1 interface pin functions (cont?d) pin no. symbol input ( i ) output ( o ) supply ( s ) function
pef 3452 te3-liu v1.3 pin descriptions preliminary data sheet 10 2001-12-05 preliminary global clock reference 29 refclk i reference clock refclk is the basic internal clock. it must be stable during reset and operation. this clock is also used to synchronize the receive pll in case of no signal. the clock frequency depends on the target application: ds3: 44.736 mhz sts-1: 51.840 mhz e3: 34.368 mhz to fulfill e.g., itu-t g.832 a clock accuracy of 20 ppm is required. 39 xtal1 i j itter attenuation reference connection for an external pullable crystal. ds3: 14.912 mhz sts-1: 17.280 mhz e3: 11.456 mhz if jitter attenuation is disabled (default), xtal1 is internally driven to a fixed level (not floating). 38 xtal2 o table 1 interface pin functions (cont?d) pin no. symbol input ( i ) output ( o ) supply ( s ) function
pef 3452 te3-liu v1.3 pin descriptions preliminary data sheet 11 2001-12-05 preliminary table 2 control pin functions pin no. symbol input ( i ) output ( o ) supply ( s ) function 33 res i hardware reset a low signal at this pin forces the device into reset state. 23 cs i + pu chip select 0 = hardware control signals are switched through 1 = hardware control signals are ignored 5ds3/e3 i + pu ds3/sts-1 or e3 select primary mode selection. this signal has to be stable during reset and may not change afterwards. it must not be connected to a pbus. 0 = e3 1 = ds3 or sts-1 (see ds3/sts-1 ) 4ds3/sts-1 i + pu ds3 or sts-1 select primary mode selection. this signal has to be stable during reset and may not change afterwards. it must not be connected to a pbus. 0 = sts-1 1 = ds3 13 lcode i + pu line code select for receive and transmit direction e3: 0 = ami 1 = hdb3 ds3/sts-1: 0 = ami 1 = b3zs 16 xais i + pu transmit alarm indication 0 = no ais 1 = ais all-ones insertion
pef 3452 te3-liu v1.3 pin descriptions preliminary data sheet 12 2001-12-05 preliminary 20 rl i + pu remote loop switching 0 = no loop 1 = remote loop 1) 19 ll i + pu local loop switching 0 = no loop 1 = local loop 1) 21 xlt i + pu transmitter inactive 0 = transmitter enabled 1 = transmitter disabled (outputs 1.5 v common mode voltage) 14 mon i + pu line monitoring mode 0 = additional 20 db gain at rl1/rl2 1 = normal 15 ble i + pu b lanking enable 0 = detected signal is switched through even in case of los 1 = all-zero signal is sent on rdop/rdon in case of los, refclk is used to drive rclk 12 dr/sr i + pu dual rail/single rail select the framer interface is operated either in dual rail or single rail mode. in single rail mode, the bpv signal is output on rdon/ bpv and input on xdin is ignored. 0 = single rail 1 = dual rail 6rpei + pu rcl k positive edge selection 0 = rdop, rdon are clocked with negative (falling) edge of rclk 1 = rdop, rdon are clocked with positive (rising) edge of rclk 7 xpe i + pu x cl k positive edge selection 0 = xdip, xdin are clocked with negative (falling) edge of xclk 1 = xdip, xdin are clocked with positive (rising) edge of xclk table 2 control pin functions (cont?d) pin no. symbol input ( i ) output ( o ) supply ( s ) function
pef 3452 te3-liu v1.3 pin descriptions preliminary data sheet 13 2001-12-05 preliminary 43 jatt i + pd j itter attenuation enable this signal has to be stable during reset and may not change afterwards. it must not be connected to a pbus. 0 = no jitter attenuation (default if left open) 1 = jitter attenuation in transmit direction 22 los o loss of signal indication 0 = correct signal 1 = loss of signal los is synchronized on rclk. during los, a clock signal is generated internally anddrivenonrclk. 1) if rl = ll = 1, the device is set into power down mode. table 2 control pin functions (cont?d) pin no. symbol input ( i ) output ( o ) supply ( s ) function
pef 3452 te3-liu v1.3 pin descriptions preliminary data sheet 14 2001-12-05 preliminary table 3 power supply pins pin no. symbol input ( i ) output ( o ) supply ( s ) function 11 v ddr s (analog) positive power supply for the analog receiver 8v ssr s (analog) power supply ground for the analog receiver 44 v ddx s (analog) positive power supply for the analog transmitter 2v ssx s (analog) power supply ground for the analog transmitter 18 v ddrp s (analog) positive power supply for the analog receiver pll 17 v ssrp s (analog) power supply ground for the analog receiver pll 37 v ddxp s (analog) positive power supply for the analog transmitter pll 40 v ssxp s (analog) power supply ground for the analog transmitter pll 27 v dd s positive power supply for digital subcircuits and the digital receiver output 28 v ss s power supply ground for digital subcircuits and the digital receiver output
pef 3452 te3-liu v1.3 pin descriptions preliminary data sheet 15 2001-12-05 preliminary note: pu = input or input/output comprising an internal pullup device pd = input or input/output comprising an internal pulldown device to override the internal pullup (pulldown) by an external pulldown (pullup), a resistor value of 47 k ? is recommended. unused pins containing pullups or pulldowns can be left open. table 4 test pins 1 ) 1) these pins are used for factory test only ; boundary scan mode is not provided. pin no. symbol input ( i ) output ( o ) supply ( s ) function 34 trs i + pu tap controller reset active low test controller reset ; this pin must be connected to rst or v ss 35 tdi i + pu test data input 36 tms i + pu test mode select 41 tck i + pu test clock 42 tdo o test data output
pef 3452 te3-liu v1.3 functional description preliminary data sheet 16 2001-12-05 preliminary 3 functional description 3.1 functional overview the te3-liu? device contains analog and digital functional blocks, which are configured and controlled by direct hardware or microprocessor control. the main interfaces are receive line interface transmit line interface framer interface hardware interface the main internal functional blocks are analog line receiver with noise & crosstalk filter, equalizer network and clock/data recovery analog line driver with programmable pulse shaper central clock generation module jitter attenuator maintenance functions (e.g., loop switching local or remote) hardware/microprocessor control interface
pef 3452 te3-liu v1.3 functional description preliminary data sheet 17 2001-12-05 preliminary 3.2 b lock diagram figure 6 b lock diagram alos detection los detection decoder encoder noise filter equalizer local loop remote loop transmit pll line driver & lbo pulse shaper test mode control hardware/ p interface rl1 rl2 res tdi tms tck rclk rdop xclk xdip xdin general control rdon/bpv mon xais los dr/sr lcode ds3/sts1/e3 20 db gain stage var. gain amplifier level detection autom. gain control clock & data recovery refclk ds3/e3 ais insertion trs tdo rl ll xlt los los, ble dr/sr lcode ds3/sts1/e3 jitter attenuator buffer jitter attenuator pll f0231 xtal1 xtal2 jatt xl1 xl2 mode control ds3/sts-1 jatt refclk xais lcode xpe rpe xlt mon ll rl dr/sr ble cs
pef 3452 te3-liu v1.3 functional description preliminary data sheet 18 2001-12-05 preliminary 3.3 functional b locks 3.3.1 hardware control unit all hardware control signals except ds3/e3 ,ds3/sts-1 and jatt are gated by cs .all other control signals are gated by cs to allow an easy connection to a microprocessor ( p) data bus. ds3/e3 ,ds3/sts-1 and jatt may not be connected to a data bus. if direct hardware control without p is intended, cs has to be connected to v ss . after reset all control input values are cleared. the default control values (driven by internal pullups) are activated after cs = low is applied for the first time after reset. table 5 hardware control functions device function control signal selection of e3 or ds3/sts-1 mode 1) ds3/e3 0 = e3 1 = ds3 or sts-1 2) selection of ds3 or sts-1 mode 1) ds3/sts-1 0 = sts-1 1 = ds3 2) this pin is ignored, if e3 mode is selected by ds3/e3 = 0 dual rail select dr/sr 0 = single rail data on rdop and xdip 1 = dual rail data on rdop/rdon and xdip/xdin 2) receive clock edge selection rpe 0 = data change on negative edge 1 = data change on positive edge 2) transmit clock edge selection xpe 0 = data change on negative edge 1 = data change on positive edge 2) selection of line coding lcode 0 = ami 1 = hdb3 (e3) 2) 1 = b3zs (ds3/sts-1) 2) send ais (all-ones alarm indication signal) xais 0 = no insertion 1 = ais insertion 2)
pef 3452 te3-liu v1.3 functional description preliminary data sheet 19 2001-12-05 preliminary select remote loop rl 0 = normal operation 1 = remote loop select local loop ll 0 = normal operation 1 = local loop select power down mode ll & rl 00 = normal operation 01 = remote loop operation 10 = local loop operation 11 = power down 2) blanking enable ble 0 = data signal is switched through even in case of los 1 = all-zero signal is transmitted on rdop/rdon in case of los using rclk derived from refclk 2) line monitoring mode mon 0 = additional 20 db gain stage activated 1 = normal amplifier setting 2) transmitter inactive mode xlt 0 = normal operation 1 = inactive 2)3)4) jitter attenuation enable jatt 0 = jitter attenuation disabled 2) 1 = jitter attenuation enabled 1) to be selected while reset is active (rst = 0) 2) default, if pin is left open and cs has been asserted at least once 3) outputs 1.5 v common mode voltage 4) connecting of cs to vss or asserting cs in parallel to res suppresses spurious output on xl1/2 table 5 hardware control functions (cont?d) device function control signal
pef 3452 te3-liu v1.3 functional description preliminary data sheet 20 2001-12-05 preliminary table 6 hardware indication signals device function indication signal indicate los (loss of signal) los 0 = normal signal 1 = loss of signal indicate bpv (bipolar violation) bpv 0 = no violation 1 = bipolar violation available in single rail mode only on pin rdon/bpv.
pef 3452 te3-liu v1.3 interface description preliminary data sheet 21 2001-12-05 preliminary 4 interface description 4.1 receiver 4.1.1 standard receiver application figure 7 receiver configuration the external components are the same for ds3, sts-1 and e3 applications. table 7 external component values for receiver parameter characteristic line impedance [ ? ] ds3 sts-1 e3 75 r 1 ( 1 % ) [ ? ] 75 c 1 ( 20 % ) [ nf ] 100 t 2 : t 1 1:1 te3-liu tm rl1 r1 rl2 1:1 c1 75 ? f0080
pef 3452 te3-liu v1.3 interface description preliminary data sheet 22 2001-12-05 preliminary 4.1.2 line monitoring application figure 8 ds3 line monitoring the external components are according to ansi t1.102 annex b. the dimensions given above lead to a signal level at the monitor device input of approximately -20 db below the level at the receiver device. similar configurations using the line monitoring mode are possible in sts-1 or e3 applications. table 8 external component values for ds line monitoring parameter values r 1 ( 1 % ) [ ? ] 75 r 2 ( 1 % ) [ ? ] 47 r 3 ( 1 % ) [ ? ] 470 c 1 ( 20 % ) [ nf ] 100 t 2 : t 1 1:1 f0081 r2 c1 te3-liu tm receiver mode te3-liu tm monitor mode rl1 mon = 1 mon = 0 r3 rl2 rl1 rl2 1:1 1:1 dsx cross connect point r1 c1 75 ? 75 ?
pef 3452 te3-liu v1.3 interface description preliminary data sheet 23 2001-12-05 preliminary 4.1.3 receive line interface the receive line interface consists of a pre-amplifier, a noise and crosstalk filter, a variable gain amplifier and an equalizer followed by the clock and data recovery. the noise and crosstalk filter reduces distortions within the incoming analog signal. the vga amplifies the analog signal and the equalizer compensates the frequency dependent line attenuation. digital signal levels are formed within the retiming block of the clock and data recovery. receive return loss requirements of itu-t g.703 are fulfilled as required for e3 operation. the equalizer contains an additional 20 db gain stage, which is used in line monitoring mode to amplify resistively attenuated signals. figure 9 receive clock system table 9 e3 receive return loss fre q uency range return loss from [ khz ] to [ khz ][ d b] 860 1720 12 1720 34368 18 34368 51550 14 f0094 v1.3 noise & crosstalk filter variable gain amplifier receive pll mon rl1 rl2 dual rail receive data 20 db gain stage equalizer automatic gain control level detection retiming receive clock false lock detection reference clock
pef 3452 te3-liu v1.3 interface description preliminary data sheet 24 2001-12-05 preliminary 4.1.4 receive clock and data recovery the receive clock and data recovery extracts the route clock rclk from the digital data stream and converts the data stream into a dual rail bit stream. the clock and data recovery needs a reference clock to keep the pll stable during times without data signal at rl1/rl2. the clock that is output on pin rclk is the recovered clock of the signal provided on rl1/rl2 and has a duty cycle close to 50 % . the intrinsic jitter generated in the absence of any input jitter is defined in chapter 4.1.8 . the pll reference clock is generated internally without the need for external components. 4.1.5 receive line coding in e3 applications the hdb3 and the ami coding is provided for the data received from the ternary interface. in ds3/sts-1 mode the b3zs and ami code is supported. in b3zs or ami code all code violations are detected and indicated. 4.1.5.1 ami code the ami code is defined as a dual rail data signal, where the combinations 00 ( " 0 " ), 10 ( "+ 1 " ) and 01 ( " -1 " ) are valid. no subsequent "+ 1 " or " -1 " bits are allowed, these will be detected as bipolar violations and indicated on pin rdon/bpv, if single rail mode is selected (according to ansi t1.231 chapter 7.1). the received ami data stream is either switched transparently to the framer interface as dual rail data or converted into a single rail data stream. 4.1.5.2 b 3 z scode in the b3zs line code each block of three consecutive zeros is replaced by either of two replacements codes which are b0v and 00v, where b represents a pulse which applies to the bipolar rule ( "+ 1 " or " -1 " ) and v represents a bipolar violation (two consecutive "+ 1 " or " -1 " bits). the replacement code is chosen in a way that there is an odd number of valid b pulses between consecutive v pulses to avoid the introduction of a dc component into the analog signal. the receive line decoder decodes the incoming b3zs data signal and changes the replacement patterns to the original three-zeros pattern. pattern sequences violation these rules are reported as bipolar violation errors. data output to the framer interface can be selected to be either dual rail or single rail.
pef 3452 te3-liu v1.3 interface description preliminary data sheet 25 2001-12-05 preliminary 4.1.5.3 hd b 3code in the hdb3 line code each block of four consecutive zeros is replaced by either of two replacements codes which are b00v and 000v, where b represents a pulse which applies to the bipolar rule ( "+ 1 " or " -1 " ) and v represents a bipolar violation (two consecutive "+ 1 " or " -1 " bits). the replacement code is chosen in a way that there is an odd number of valid b pulses between consecutive v pulses to avoid the introduction of a dc component into the analog signal. the receive line decoder decodes the incoming hdb3 data signal and changes the replacement patterns to the original three-zeros pattern. pattern sequences violation these rules are reported as bipolar violation errors. data output to the framer interface can be selected to be either dual rail or single rail. 4.1.6 alarm handling the receive line interface includes the alarm detection for loss of signal (los). los is indicated either if an analog or a digital loss of signal condition is detected. during los a clock signal is sent on rclk. the clock is internally derived from refclk. 4.1.6.1 ds3 los definition detection and recovery of digital los defects in ds3 mode is done according to ansi t1.231: an los defect occurs when 175 contiguous pulse positions with no pulses of either positive or negative polarity at the line interface are detected. an los defect is terminated upon detecting an average pulse density of at least 33 % over a period of 175 contiguous pulse positions following the receipt of a pulse. an los defect shall not be terminated if, at the end of the pulse-position interval, any subintervals of 100 pulse positions contain no pulses of either polarity. 4.1.6.2 sts-1 los definition detection and recovery of digital los defects in sts-1 mode is defined in ansi t1.231 (chapter 8.1.2.1.1) as follows: an los defect occurs upon detection of no transitions on the incoming signal (before descrambling) for time t, where 2.3 t 100 s. the los defect is terminated after a time period equal to the greater of 125 sor2.5 t? containing no transition-free interval of length t?, where 2.3 t? 100 s.
pef 3452 te3-liu v1.3 interface description preliminary data sheet 26 2001-12-05 preliminary 4.1.6.3 e3 los definition analog los is detected, if the signal level on pins rl1/2 drops below a fixed level ( " b " ) for a certain period. loss of signal level " b " is defined to be between 15 and 35 db below normal signal level " a " . if the signal exceeds 35 db for 175 contiguous pulse periods, analog los defect is indicated. analog los defect is cleared, if the signal exceeds a threshold of 15 db below nominal level for 175 contiguous pulse periods (10 n 255). see itu-t g.775 for reference. figure 10 e3 loss of signal definition f0101 v1.2 b a seeitu-tg.775page4 level below nominal nominal value maximum cable loss 3db tolerance range, " no transition condition " or " transition condition " may be declared " transition condition " must be detected " no transition condition " must be detected 35 db 15 db 0db
pef 3452 te3-liu v1.3 interface description preliminary data sheet 27 2001-12-05 preliminary 4.1.7 j itter tolerance the te3-liu? receiver?s tolerance to input jitter complies to and exceeds the relevant international standards. especially the requirements of telcordia gr-499-core (ds3), itu-t g.824 (ds3), gr-253-core (sts-1) and itu-t g.823 (e3) are fulfilled and exceeded. figure 11 and table 10 show the different input jitter specifications. low frequency jitter is called " wander " , where the defined border between jitter and wander is 10 hz for ds3/e3 and 100 hz for sts-1. figure 11 j itter tolerance principle table 10 input j itter re q uirements reference a1a2a3f1f2f3f4f5f6 [ ui pp ][ hz ] gr-499-core, category i 50.1 not def. 10 2300 60 10 3 300 10 3 not def. not def. gr-499-core, category ii 10 0.3 not def. 10 669 22.3 10 3 300 10 3 not def. not def. gr-253-core, category ii 15 1.5 0.15 10 30 300 2 10 3 20 10 3 not def. itu-t g.823 & etsi tbr24 1.5 0.15 not def. 100 1000 10 10 3 800 10 3 not def. not def. itu-t g.824 18 s5 0.1 not def. 1.2 10 -5 10 600 30 10 3 400 10 3 input jitter amplitude jitter frequency a1 a2 f1 f2 f3 f4 fail pass f5 a3 f0085 f6
pef 3452 te3-liu v1.3 interface description preliminary data sheet 28 2001-12-05 preliminary figure 12 j itter tolerance gr-499-core j itter tolerance re q uirements ( ds3 ) the input jitter tolerance is defined as the minimum amplitude of sinusodial jitter at a given frequency that when modulating the signal at an equipment input port results in more than 2 errored seconds in a 30-second measurement interval. requirements on input jitter tolerances are then given in terms of a jitter tolerance mask, which represents the minimum acceptable jitter tolerances for a specified range of jitter frequencies. there are two different jitter tolerance masks defined for category i (sonet interfaces) and category ii (non-sonet interfaces) equipment. gr-253-core j itter tolerance re q uirements ( sts-1 ) for category i interfaces, the same requirements are used as defined in gr-499-core. for category ii interfaces that are specified as having reduced jitter tolerance, shall tolerate, as a minimum, input jitter applied according to the mask given in table 10 . 4.1.8 receive output j itter the intrinsic jitter of the receiver output signal rdop/rdon/rclk (if no input jitter is applied) is e3: < 0.06 ui ds3: < 0.08 ui sts-1: < 0.10 ui f0104 f0104 te3-liu 0,01 0,1 1 10 100 0,10 1,00 10,00 100,00 1000,00 10000,00 100000,00 1000000,00 j itter fre q uency [ hz ] j itter amplitude [ ui ] gr-499-core cat. 1 gr-499-core cat. 2 itu-t g.823 itu-t g.824 gr-253-core cat. 2 puccini pass area fail area te3-liu
pef 3452 te3-liu v1.3 interface description preliminary data sheet 29 2001-12-05 preliminary 4.2 transmitter the serial bit stream is then processed by the transmitter which has the following functions: generation of ami, b3zs (ds3/sts-1) or hdb3 (e3) coded signals all-ones generation (alarm indication signal) 4.2.1 transmit line interface the received data stream on pins xdip (single rail data) or xdip/xdin (dual rail data) is converted into a ternary signal which is output on pins xl1 and xl2. in e3 mode the hdb3 and ami line code are supported, in ds3/sts-1 mode the b3zs and ami is supported. figure 13 transmitter configuration the external components are the same for ds3, sts-1 and e3 applications. transmit return loss requirements for e3 defined in ets 300 166 are fulfilled. pulse mask table 11 external component values for transmitter parameter characteristic line impedance [ ? ] ds3 sts-1 e3 75 r 1 ( 1 % ) [ ? ] 37.5 1) 1) this value refers to an ideal transformer without any parasitics. any transformer resistance or other parasitic resistances have to be taken into account when calculating the final value for the output serial resistors. c p [ pf ] 37 2) 2) this value includes all parasitic capacitances on the secondary side of the transformer. t 2 : t 1 1:1 te3-liu tm xl1 r1 xl2 t1 : t2 r1 c p f0079 75 ?
pef 3452 te3-liu v1.3 interface description preliminary data sheet 30 2001-12-05 preliminary requirements according to ansi t1.102 (at cross connect point, up to 450 ft.) are fulfilled. note: an additional capacitor on the primary or secondary side of the transformer may be required in some applications to improve the pulse mask, if the parasitic capacitances of the pcb are very small. 4.2.2 transmit clock system the supplied transmit clock xclk is duty-cycle corrected by an internal pll circuit to providea50 % clock signal to the internal line driver unit. the pulse shaper working frequency is fourfold of the xclk frequency. if the transmit clock xclk is failing, an all-zero signal is generated automatically. if ais insertion is selected, the output signal is referenced to refclk. figure 14 transmit clock system table 12 e3 transmit return loss fre q uency range return loss 1 ) 1) measured with an unframed prbs 2 15 -1 pattern from [ khz ] to [ khz ][ d b] 860 1720 6 1720 51550 8 encoder line driver pulse shaper xl2 xl1 xclk xdip xdin transmit pll refclk xais disable testmode ais insertion xais f0232 jitter attenuator buffer jitter attenuator pll xtal1 xtal2 jatt f nom x4 f no m f nom f nom :3 f nom
pef 3452 te3-liu v1.3 interface description preliminary data sheet 31 2001-12-05 preliminary 4.2.3 j itter attenuation jitter is reduced in transmit direction, if the jitter attenuator is activated (jatt = 1). the jatt control signal enables/disables the jitter attenuation pll and activates/bypasses the buffer. the jitter attenuator consists of a buffer and a pll. the jitter attenuation pll delivers a " jitter free " clock (nominal frequency divided by 3, see table 13 )tothetransmitpll which generates the buffer read clock. the jitter attenuation pll uses a pullable crystal and supports a tuning range of 150 ppm. the jitter attenuator uses a 64-bit dual rail buffer and fulfills the requirements of gr-499- core and gr-253-core as shown in figure 15 . this covers the requirements of itu- t g.751, g.752 and g.755 as well. to avoid the need for a high frequency crystal, the reference clock for the jitter attenuation pll is only one third of the nominal frequency. a detailed block diagram of the transmit clocking is given in figure 14 . further requirements for the external crystal are found in table 21 on page 45 . table 13 j itter attenuation pll operation fre q uencies operation mode j itter attenuation pll input fre q uency j itter attenuation pll output fre q uency crystal fre q uency ds3 44.736 mhz 14.912 mhz 14.912 mhz sts-1 51.840 mhz 17.280 mhz 17.280 mhz e3 34.368 mhz 11.456 mhz 11.456 mhz
pef 3452 te3-liu v1.3 interface description preliminary data sheet 32 2001-12-05 preliminary figure 15 j itter attenuation characteristic 4.2.4 intrinsic j itter the te3-liu? transmit pll generates an output jitter which fulfills the requirements as specified in table 14 below. table 14 transmit output j itter specification measurement filter b andwidth output j itter 1 ) 1) measured with maximum input jitter applied (see figure 12 ). lower cutoff upper cutoff gr-499-core (ds3) 10 hz 300 khz < 1.0 ui pp < 0.3 ui rms ansi t1.404 (ds3) 10 hz 400 khz < 0.5 ui pp 30 khz 400 khz < 0.05 ui pp gr-253-core (sts-1) 12 khz 400 khz < 1.0 ui pp < 0.3 ui rms etsi tbr24 (e3) 100 hz 800 khz < 0.4 ui pp 10 khz 800 khz < 0.15 ui pp f0141 0.1 db -20db -40db 10 100 1000 10000 100000 jitter frequency jitter gain 15000 20 db/decade te3-liu 40 gr-253-core gr-499-core 0.5 db 300 itu-t g.751 itu-t g.752 itu-t g.755 &
pef 3452 te3-liu v1.3 interface description preliminary data sheet 33 2001-12-05 preliminary 4.2.5 pulse shaper the internal pulse shaper generates the required pulse shapes for e3, ds3 and sts-1 signals according to ansi t1.102, t1.404, telcordia gr-499-core and itu-t g.703). the specific pulse mask is fulfilled at the crossconnect point at a distance of 0 to 450 ft. to the transmitter (ds3 requirement). the maximum line length between a te3-liu? transmitter and te3-liu? receiver is 1100 ft. for a coaxial cable of at & t type 728a, 734a or 734d. 4.2.6 transmit line coding 4.2.6.1 ami code the ami code is defined as a dual rail data signal, where the combinations 00 ( " 0 " ), 10 ( "+ 1 " ) and 01 ( " -1 " ) are valid. additionally no subsequent "+ 1 " or " -1 " bits are allowed (bipolar violations). a dual rail data stream is passed transparently, even if it contains bipolar violations. a single rail data stream is encoded to a correct ami coded bipolar data stream without zero code suppression. 4.2.6.2 b 3 z scode in the b3zs line code each block of three consecutive zeros is replaced by either of two replacements codes which are b0v and 00v, where b represents a pulse which applies to the bipolar rule ( "+ 1 " or " -1 " ) and v represents a bipolar violation (two consecutive "+ 1 " or " -1 " bits). the replacement code is chosen in a way that there is an odd number of valid b pulses between consecutive v pulses to avoid the introduction of a dc component into the analog signal. the transmit line encoder detects three-zeros pattern sequences and changes them to the appropriate replacement pattern. although b3zs coding is normally used with single rail nrz data, the transmit line encoder accepts either dual rail or single rail data. bipolar violations in an incoming dual rail data stream are converted to valid data pulses. 4.2.6.3 hd b 3code in the hdb3 line code each block of four consecutive zeros is replaced by either of two replacements codes which are b00v and 000v, where b represents a pulse which applies to the bipolar rule ( "+ 1 " or " -1 " ) and v represents a bipolar violation (two consecutive "+ 1 " or " -1 " bits). the replacement code is chosen in a way that there is an odd number of valid b pulses between consecutive v pulses to avoid the introduction of a dc component into the analog signal. the transmit line encoder detects three-zeros pattern sequences and changes them to the appropriate replacement pattern.
pef 3452 te3-liu v1.3 interface description preliminary data sheet 34 2001-12-05 preliminary although hdb3 coding is normally used with single rail nrz data, the transmit line encoder accepts either dual rail or single rail data. bipolar violations in an incoming dual rail data stream are converted to valid data pulses. 4.2.7 ais insertion an unframed all-ones signal can be inserted into the transmitted data stream. to fulfill the required accuracy, a reference clock of 20 ppm is needed on pin refclk. if local loop configuration and ais insertion is selected together, the ais signal is looped back to rdop/rdon. 4.3 framer interface the interface to the receive framer is realized by rdop, rdon and rclk. data at rdop/n are clocked off with either the rising (rpe = 1) or falling edge (rpe = 0) of rclk. alternatively a single rail signal can be selected to be output on pin rdop (dr/sr = 0). bipolar violation indications are output on pin rdon/bpv in this case. data from the framer interface are sampled at xdip and xdin on the active edge of the xclk. the active edge can be the rising (xpe = 1) or falling edge (xpe = 0) of xclk. alternatively a single rail signal can be used on pin xdip (dr/sr = 0). note: selection of dual rail/single rail mode is common to receive and transmit direction. see figure 24 on page 47 and figure 25 on page 48 for details.
pef 3452 te3-liu v1.3 interface description preliminary data sheet 35 2001-12-05 preliminary 4.4 maintenance functions 4.4.1 remote loop in the remote loopback mode the clock and data recovered from the line inputs rl1/2 are routed back to the line outputs xl1/2. as in normal mode they are also processed by the synchronizer and then sent to the framer interface. data passes the decoder and encoder circuit. the recovered receive clock is used to drive the transmit pulse shaper. figure 16 remote loop signal flow note: if remote loop and local loop are selected simultaneously, the device will be set into power down mode. note: the jitter attenuator can be switched off optionally. f0083 noise & crosstalk filter rl1 equalizer rl2 clock & data recovery decoder remote loop encoder jitter attenuator pulse shaper line driver xl1 xl2 rdon rdop rclk xdin xdip xclk
pef 3452 te3-liu v1.3 interface description preliminary data sheet 36 2001-12-05 preliminary 4.4.2 local loop the local loopback mode disconnects the receive lines rl1/2 from the receiver. instead of the signals coming from the line data provided by system interface is routed through the analog receiver back to the framer interface. the transmit bit stream is sent to the transmit line unchanged. if xais = 1 is selected, the transmit data stream is replaced by an all-ones signal and looped back. figure 17 local loop signal flow note: if remote loop and local loop are selected simultaneously, the device will be set into power down mode. note: the jitter attenuator can be switched off optionally. f0084 noise & crosstalk filter rl1 equalizer rl2 clock & data recovery decoder local loop encoder jitter attenuator pulse shaper line driver xl1 xl2 rdon rdop rclk xdin xdip xclk
pef 3452 te3-liu v1.3 operational description preliminary data sheet 37 2001-12-05 preliminary 5 operational description 5.1 operational overview the te3-liu? can be operated in three principle modes, which are either e3, ds3 or sts-1 mode. this basic operation mode selection has to be stable before the reset signal goes inactive. the device is programmable by pin selection. direct connection to a microprocessor data bus is possible by using the chip select pin (cs ) as a write strobe. 5.2 device reset the te3-liu? is forced to the reset state if a low signal is input on pin res (for minimum period see page 42 ). during reset, all output stages are in a high impedance state, all internal flip-flops are reset. the basic device mode (ds3, sts-1 or e3, jitter attenuation) has to be selected during reset to enable the internal plls to adjust. after reset all control input values are cleared. the default control values (driven by internal pullups) are activated after cs = low is applied for the first time after reset. 5.3 device power down the te3-liu? can be set into power down state to reduce power consumption, if not active. power down mode is selected by setting rl = ll = 1. receive and transmit circuits are switched off including internal plls and transmit line driver. recovery from power down mode is achieved by clearing either of rl or ll (rl = 0and/orll = 0). after recovery from power down, the internal plls need to stabilize again. refclk must be active to recover from power down mode. internal pullup resistors are not switched off during power down to prevent open input lines from floating. note: if switching directly from local loop to remote loop or vice versa, make sure that there is no signal overlap, which would set the device into power down mode unintentionally. 5.4 transmit line inactive if the transmitter is not used, it can be switched into inactive mode by setting xlt = 1. during inactive state the common mode voltage of 1.5 v is output on xl1 and xl2. the transmit pll is not stopped and output can be enabled again by xlt = 0 without wait time.
pef 3452 te3-liu v1.3 electrical characteristics preliminary data sheet 38 2001-12-05 preliminary 6 electrical characteristics 6.1 absolute maximum ratings note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 15 maximum ratings parameter symbol limit values unit ambient temperature under bias t a ?40to85 c storage temperature t stg ?65to150 c ic supply voltage (digital) v dd ? 0.4 to 4.5 v ic supply voltage receive (analog) v ddr ? 0.4 to 4.5 v ic supply voltage transmit (analog) v ddx ? 0.4 to 4.5 v voltage on any output pin with respect to ground v so ? 0.4 to 4.5 v voltage on any input pin with respect to ground v si ? 0.4 to 5.5 v esd robustness 1) hbm: 1.5 k ? , 100 pf 1) according to mil-std 883d, method 3015.7 and esd ass. standard eos/esd-5.1-1993. v esd,hbm 2000 v
pef 3452 te3-liu v1.3 electrical characteristics preliminary data sheet 39 2001-12-05 preliminary 6.2 operating range note: in the operating range, the functions given in the circuit description are fulfilled. all v dd pins have to be connected to the same voltage level, all v ss pins have to be connected to ground level. note: typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a =25 c and 3.3v supply voltage. table 16 power supply range parameter symbol limit values unit condition min. max. ambient temperature t a -40 85 c supply voltage v dd v ddr v ddx v ddrp v ddxp 3.13 3.46 v 3.3 v 5 % digital input voltages v id 05.25v5.0v + 5 % ground v ss v ssr v ssx v ssrp v ssxp 00v
pef 3452 te3-liu v1.3 electrical characteristics preliminary data sheet 40 2001-12-05 preliminary 6.3 dc characteristics table 17 dc parameters parameter symbol limit values unit notes min. max. input low voltage v il ?0.4 0.8 v input high voltage v ih 2.0 5.25 v output low voltage v ol 0.45 v i ol =+ 4ma 1) output high voltage v oh 2.4 v i oh = ?4ma 1) average power supply current i dd 110 (typ.) ma typical (ds3, prbs, jatt enabled, 3.3 v) 155 (typ.) worst case (sts-1, jatt enabled, ais, 3.46 v) input leakage current i il11 1 a v in =v dd 2) input leakage current i il12 1 a v in =v ss 2) input pullup current i ipu 225 a v in =v ss 5(typ.) input pulldown current i ipu ?2 ?25 a v in =v dd -5 (typ.) transmitter leakage current i tl 1 ma xl1/2 = v ddx , xlt = 1 1 ma xl1/2 = v ssx , xlt = 1 200 a xl1/2 = 1.50 v 3) , xlt = 1 transmitter output impedance r x 5(typ.) ? applies to xl1and xl2 4) differential peak voltage of a mark (at xl1/xl2) v x 2.0 v receiver differential peak voltage of a mark (at rl1/rl2) v r v ddr + 0. 3 vrl1,rl2 receiver input impedance z r tbd. k ? 3)
pef 3452 te3-liu v1.3 electrical characteristics preliminary data sheet 41 2001-12-05 preliminary receiver sensitivity s rsh 0 tbd. db rl1, rl2 analog loss of signal threshold e3 v los3 -35 ? 15 db 1) applies to all output pins except analog pins xl1/xl2 2) input leakage currents of pins containing internal pullup devices are measured in a testmode which switches off the pullups. 3) test against common mode voltage, parameter not tested in production 4) parameter not tested in production table 17 dc parameters (cont?d) parameter (cont?d) symbol limit values unit notes min. max.
pef 3452 te3-liu v1.3 electrical characteristics preliminary data sheet 42 2001-12-05 preliminary 6.4 ac characteristics 6.4.1 reset figure 18 reset timing note: refclk must be active during reset. table 18 reset timing parameter values no. parameter limit values unit min. max. 1res pulse width low 10 s 2ds3/e3 ,ds3/sts-1 , jatt to res setup time 5ns 3 pll startup time 1000 s f0095 1 2 ds3/e3 ds3/sts-1 jatt (plls tuned) 3 res
pef 3452 te3-liu v1.3 electrical characteristics preliminary data sheet 43 2001-12-05 preliminary 6.4.2 reference clock figure 19 reference clock timing table 19 refcl k timing parameter values no. parameter limit values unit min. typ. max. 1 refclk period e3 29.1 ns refclk period ds3 22.4 ns refclk period sts-1 19.3 ns 2refclkhigh 20 80 % 3 refclk low 20 80 % 4 refclk rise time 4 1) 1) not tested in production ns 5refclkfalltime 4 1) ns clock accuracy 20 2) 2) if ds3-ais function is not required, 200 ppm is sufficient to guarantee correct receive pll function ppm f0107 refclk 2 3 1 4 5
pef 3452 te3-liu v1.3 electrical characteristics preliminary data sheet 44 2001-12-05 preliminary 6.4.3 j itter attenuator reference clock figure 20 x tal clock timing figure 21 recommended crystal circuit table 20 x tal timing parameter values no. parameter limit values unit min. typ. max. 1 xtal1/2 period e3 87.29 ns xtal1/2 period ds3 67.06 ns xtal1/2 period sts-1 57.87 ns f0164 xtal1 2 3 1 4 5 f0245 te3-liu tm c l c l ds3: sts-1: e3: 14.912 mhz 17.280 mhz 11.456 mhz xtal1 xtal2
pef 3452 te3-liu v1.3 electrical characteristics preliminary data sheet 45 2001-12-05 preliminary figure 22 crystal pulling range note: c leff =c lext +c lint +c lpara c lext = 0.5 x c l table 21 x tal crystal parameter values no. parameter limit values unit min. typ. max. 1 crystal nominal frequency ds3 14.912 mhz crystal nominal frequency sts-1 17.280 mhz crystal nominal frequency e3 11.456 mhz 2 crystal motional capacitance c 1 25 ff 3 crystal shunt capacitance c 0 7pf 4 crystal load capacitance c leff 1) 1) this value includes the capacitance of the external capacitors (c lext ) plus all internal (c lint ) and external parasitic capacitances (c lpara ). the value of the external capacitor has to be chosen depending on the printed circuit board layout. a typical value for c l is0to10pf,c l should be adapted to the parasitics to achieve a symmetrical pulling range. 15 pf 5 crystal resonance resistance r r 30 ? 6 internal parasitic load capacitance c lint 7.5 pf f0259 0 -50 -100 -150 -200 + 50 + 100 + 150 + 200 15 load capacitance c leff [ pf ] f-f 0 f 0 [ ppm ] pulling range 20 10 nominal value
pef 3452 te3-liu v1.3 electrical characteristics preliminary data sheet 46 2001-12-05 preliminary 6.4.4 microprocessor control figure 23 chip select timing table 22 chip select timing parameter values no. parameter limit values unit min. max. 1cs pulse width low 2.5 t rclk e1 73 ns ds3 56 ns sts-1 50 ns 2cs pulse width high 2.5 t rclk e1 73 ns ds3 56 ns sts-1 50 ns 3 control signal setup time 10 ns 4 control signal hold time 10 ns f0097 cs 1 3 control signal 4 2
pef 3452 te3-liu v1.3 electrical characteristics preliminary data sheet 47 2001-12-05 preliminary 6.4.5 transmit input timing figure 24 x cl k input timing table 23 x cl k timing parameter values no. parameter limit values unit min. typ. max. 1 xclk period e3 29.1 ns xclk period ds3 22.4 ns xclk period sts-1 19.3 ns 2xclkhigh 30 70 % 3 xclk low 30 70 % 4 xdip, xdin setup time 2 ns 5 xdip, xdin hold time 2 ns 6 xdip, xdin, xclk rise time 1 1) 1) not tested in production ns 7 xdip, xdin, xclk fall time 1 1) ns 8 clock accuracy 20 2) 2) if ds3-ais function is not required, 200 ppm is sufficient to guarantee correct pll function ppm f0090 xclk (xpe = 0) xclk (xpe = 1) xdip, xdin 4 5 2 3 1 data change edge 7 6
pef 3452 te3-liu v1.3 electrical characteristics preliminary data sheet 48 2001-12-05 preliminary 6.4.6 receive output timing figure 25 rcl k output timing table 24 rcl k timing parameter values no. parameter limit values unit min. typ. max. 1 rclk period e3 29.1 1) 1) applies only while the receiver pll is locked to a valid signal on rl1/rl2, e.g., not in case of los ns rclk period ds3 22.4 1) ns rclk period sts-1 19.3 1) ns 2 rclkhigh 405060 % 3 rclk low 40 50 60 % 4 rdop, rdon delay time 0 1 2 2) ns 5 rdop, rdon, rclk rise time 2 5 2) 2) not tested in production ns 6 rdop, rdon, rclk fall time 2 5 2) ns f0108 rclk (rpe = 0) rclk (rpe = 1) rdop, rdon 4 2 3 1 data change edge 5 6
pef 3452 te3-liu v1.3 electrical characteristics preliminary data sheet 49 2001-12-05 preliminary 6.4.7 pulse templates 6.4.7.1 pulse template e3 figure 26 e3 pulse shape at transmitter output table 25 e3 pulse mask 1 ) 1) measured at the output port without transmission line and 75 ? load ; bit sequence: 0000000( + 1)0000000(-1)0000000( + 1)0000000(-1)... no. parameter limit values unit min. typ. max. nominal peak voltage of a mark (pulse) 1.0 v peak voltage of a space (no pulse) - 0.1 0.1 v nominal pulse width 14.55 ns amplitude ratio of positive to negative pulses 2) 2) at the center of a pulse interval 0.95 1.05 pulsewidthratioofpositivetonegativepulses 3) 3) at the nominal half amplitude 0.95 1.05 f0076 17 ns 0 t1818860-9 2 v nominal pulse figure 17/g.703 pulse mask at the 34 368-kbit/s interface (14.55 + 2.45) 8.65 ns (14.55 ? 5.90) 14.55 ns 12.1 ns (14.55 ? 2.45) 24.5 ns (14.55 + 9.95) 0.1 0.1 0.2 0.2 0.1 0.1 0.1 0.1 0.2 29.1 ns (14.55 + 14.55) 0.5 1.0
pef 3452 te3-liu v1.3 electrical characteristics preliminary data sheet 50 2001-12-05 preliminary 6.4.7.2 pulse template ds3 figure 27 ds3 pulse shape at the cross connect point ( 450 ft. ) table 26 ds3 pulse mask ( ansi t1.404, gr-499-core ) 1 ) 1) bit sequence: 0000000( + 1)0000000(-1)0000000( + 1)0000000(-1)... absolute voltage level ( 100 % value ) min. max. 0.36 v 0.85 v normalized amplitude 1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 -1.0 -0.5 0 0.5 1.0 1.5 time [ unit intervals ] f0077 gr-499-core ansi t1.404
pef 3452 te3-liu v1.3 electrical characteristics preliminary data sheet 51 2001-12-05 preliminary table 27 ds3 pulse mask ( ansi t1.404 ) lower curve time e q uation t -0.36 -0.03 -0.36 t + 0.36 t + 0.36 -0.03 upper curve time e q uation t -0.68 + 0.03 -0.68 t + 0.36 t + 0.36 table 28 ds3 pulse mask ( gr-499-core ) lower curve time e q uation -0.85 t -0.36 -0.03 -0.36 t + 0.36 + 0.36 t + 1.4 -0.03 upper curve time e q uation -0.85 t -0.68 + 0.03 -0.68 t + 0.36 + 0.36 t + 1.4 0.5 1 2 -- - 1 t 0.18 ----------- + sin + 0.03 ? 0.5 1 2 -- - 1 t 0.34 ----------- + sin + 0.03 + 0.05 0.407 e -1.84 t 0.36 ? [] + 0.5 1 2 -- - 1 t 0.18 ----------- + sin + 0.03 ? 0.5 1 2 -- - 1 t 0.34 ----------- + sin + 0.03 + 0.08 0.407 e -1.84 t 0.36 ? [] +
pef 3452 te3-liu v1.3 electrical characteristics preliminary data sheet 52 2001-12-05 preliminary 6.4.7.3 pulse template sts-1 figure 28 sts-1 pulse shape at the cross connect point ( 450 ft. ) table 29 sts-1 pulse mask 1 ) 1) bit sequence: ( + 1)0(-1)0( + 1)0(-1)... signal power min. max. -2.7dbm + 4.7 dbm table 30 sts-1 pulse mask ( ansi t1.102 ) lower curve time e q uation -0.85 t -0.38 -0.03 -0.38 t + 0.36 + 0.36 t + 1.4 -0.03 normalized amplitude 1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 -1.0 -0.5 0 0.5 1.0 1.5 time [ unit intervals ] f0109 0.5 1 2 -- - 1 t 0.18 ----------- + sin + 0.03 ?
pef 3452 te3-liu v1.3 electrical characteristics preliminary data sheet 53 2001-12-05 preliminary upper curve time e q uation -0.85 t -0.68 + 0.03 -0.68 t + 0.26 + 0.26 t + 1.4 0.5 1 2 -- - 1 t 0.34 ----------- + sin + 0.03 + 0.1 0.61 e -2.4 t 0.26 ? [] +
pef 3452 te3-liu v1.3 electrical characteristics preliminary data sheet 54 2001-12-05 preliminary 6.5 capacitances 6.6 package characteristics figure 29 thermal b ehavior of package table 31 pin capacitances parameter symbol limit values unit notes min. max. input capacitance 1) 1) not tested in production c in 510pf output capacitance 1) c out 8 15 pf all except xl1, xl2 output capacitance 1) c out 8 20 pf xl1, xl2 table 32 package characteristic values parameter symbol limit values unit notes min. typ. max. thermal resistance 1) junction to ambient 1) r thja = (t junction -t ambient )/power not tested in production r thja 63 k/w single layer pcb, 30 % /11 m metallization, 1w, no convection thermal resistance 2) junction to case 2) r th jc = (t junction -t case )/power not tested in production r thjc 15 k/w junction temperature r j 125 c f0051
pef 3452 te3-liu v1.3 electrical characteristics preliminary data sheet 55 2001-12-05 preliminary 6.7 test configuration figure 30 input/output waveforms for ac testing note: typical characteristics are mean values expected over the production spread. if not specified otherwise, typical characteristics apply at t a =25 candv dd =3.3v. note: capacitance values include all parasitics caused by board layout, transformer etc. table 33 ac test conditions parameter symbol test values unit notes load capacitance 1 c l1 50 pf digital outputs except rdop, rdon, rclk load capacitance 2 c l2 15 pf digital outputs rdop, rdon and rclk load capacitance 3 c l3 50 pf analog line output xl1, xl2 input voltage high v ih 2.4 v all except rl1, rl2 input voltage low v il 0.4 v all except rl1, rl2 test voltage v t v dd /2 v all except xl1, xl2 output test load r l 75 5 % ? xl1, xl2 rise times t r 10 - 90 % not tested in production fall times t f 90 - 10 % f0206 device under test c l v ih v il drive levels timing test points ac test level external load v t
pef 3452 te3-liu v1.3 package outlines preliminary data sheet 56 2001-12-05 preliminary 7 package outlines p-mqfp-44-2 (plastic metric q uad flat package) gpm05622 smd = surface mounted device sorts of packing package outlines for tubes, trays etc. are contained in our data book ?package information?. dimensions in mm
pef 3452 te3-liu v1.3 appendix preliminary data sheet 57 2001-12-05 preliminary 8appendix 8.1 cable characteristics cable characteristics are defined in ansi t1.102 as shown below. figure 31 ds3 cable characteristics f0105 v1.1 office cable loss ( 450 ft. coaxial ) 0 2 4 6 8 10 12 14 110100 fre q uency [ mhz ] insertion loss [ d b] office cable insertion phase ( 450 ft. coaxial ) 0 10 20 30 40 50 60 70 80 90 110100 fre q uency [ mhz ] insertion phase [ deg ]
pef 3452 te3-liu v1.3 appendix preliminary data sheet 58 2001-12-05 preliminary 8.2 application example the following picture shows a typical application circuit (excluding surge protection). figure 32 application circuit f0233 te3-liu tm v1.3 vddr/ vssr xtal1/2 rl1/2 xl1/2 vdd/vss vddx/vssx vddxp/vssxp vddrp/ vssrp n.c. test xdip xdin xclk ds3/sts-1/e3 framer/mapper receive interface refclk reference clock control interface rdop rdon rclk los ds3/sts-1/e3 framer/mapper transmit interface ds3/sts-1/e3 receive line interface ds3/sts-1/e3 transmit line interface jitter attenuation reference receive path transmit path c l c l
pef 3452 te3-liu v1.3 preliminary preliminary data sheet 59 2001-12-05 index a ais 11 ambient temperature 38 ami 24 ansi 10, 57 applications 3, 5 b b3zs 24 buffer 31 c cable 57 clock 8, 10 clock and data recovery 24 crystal 31, 44 e edge selection 12 esd 38 external component values 21, 22 h hdb3 25 i input jitter 27 international standards 10 intrinsic jitter 24 itu-t 10 j jatt 31 jitter attenuation 10, 13, 31, 32 jitter tolerance 27, 28 l line coding 11, 24 line monitoring 12, 22 local loop 12, 36 loss of signal 13 m mil-std 883d 38 o operating range 39 output jitter 28 p package 54, 56 pll 42 p-m q fp-44-2 56 power down 37 power supply 14, 38 pulse shaper 33 pulse template ds3 50 pulse template e3 49 pulse template sts-1 52 r rclk 48 receive clock 8 receive data 8 receive line interface 8, 23 receive return loss 23 receiver 21 reference clock 10, 43 remote loop 12, 35 reset 11, 37, 42, 46 s supply voltage 39 t tap controller 15 temperature 3 thermal behaviour 54 transmit clock 9 transmit data 9 transmit line 37 transmit line interface 9, 29
pef 3452 te3-liu v1.3 preliminary preliminary data sheet 60 2001-12-05 w wander 27 x xclk 47 xtal 44
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